The concept of semiconductor integration is based on the ability to batch fabricate, at relatively low cost, large numbers of interconnected circuit elements on a single chip through the use of photolithographic techniques. It is desired to develop a method for extending similar techniques to connections between chips so that the same advantages might be realized at the next level of system interconnection. The invention described herein was developed as a rapid means of interconnecting integrated circuit chips which might be thought of as providing an alternative to putting more and more complexity onto a single chip and having the potential for eliminating entirely mechanical bonding, thus achieving a qualitative improvement in the economy, reliability, density, and electrical characteristics of interchip connections by having close chip spacing, good heat sinking, and multi-level wiring.
The problems to be resolved included how to form conductors and connect them to the aluminum chip pads and what material should be used for insulation in the dielectric layer between the chips and the wiring which could be selectively removed to provide access to the chip pads. Of concern also was the compatibility of chips and array materials with processing chemicals. Finally, it was recognized that the completed array should be capable of tolerating laboratory and industrial environments including the thermal stresses resulting from normal heat dissipation during circuit operation.
A process has been developed which achieves the above goals with the use of relatively simple procedures and inexpensive equipment. Use is made of the techniques of plastic embedment electroless metal plating, electroplating, and photoforming of plastics. Important features of the process include batch plating of connections to chips, photoforming of multiple insulating layers and conductor grooves for high density packaging, and efficient removal of heat from the chips. Processing temperatures do not exceed 70.degree.C.